1. Field of the Invention
The present invention relates generally to methods for forming microelectronic layers within microelectronic fabrications. More particularly, the present invention relates methods for forming with enhanced film thickness uniformity microelectronic layers within microelectronic fabrications.
2. Background of the Invention
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels increased, and microelectronic device and patterned microelectronic conductor layer dimensions have decreased, it has become increasingly important within the art of microelectronic fabrication to form microelectronic layers with enhanced film thickness uniformity. Of the various types of microelectronic layers which it may be desired to form with enhanced film thickness uniformity within microelectronic fabrications, it is often particularly important to form an ion implant screen layer with enhanced film thickness uniformity. An ion implant screen layer within a microelectronic fabrication is typically, but not exclusively, employed to screen dopant ions implanted into a semiconductor substrate employed within a semiconductor integrated circuit microelectronic fabrication. Among other purposes, the ion implant screen layer generally provides: (1) a contamination shield to a semiconductor substrate upon which it is formed; (2) an implanted ion scattering impediment which minimizes channeling of implanted ions within a semiconductor substrate upon which it is formed; and (3) a physical barrier inhibiting outdiffusion of implanted dopant ions from within a semiconductor substrate upon which it is formed.
Traditionally, ion implant screen layers within semiconductor integrated circuit microelectronic fabrications are formed employing a thermal oxidation of a silicon semiconductor substrate to form a silicon oxide ion implant screen layer. While silicon oxide ion implant screen layers formed employing thermal oxidation methods are generally serviceable and desirable within the art of microelectronic fabrication, silicon oxide ion implant screen layers formed employing thermal oxidation methods are nonetheless not entirely without problems in the art of microelectronic fabrication. In particular, silicon oxide ion implant screen layers formed employing thermal oxidation methods are generally formed incident to a significant thermal excursion of a silicon semiconductor substrate which may deleteriously affect a dopant profile of a pre-existing doped region formed within the silicon semiconductor substrate. While silicon oxide ion implant screen layers formed employing conventional plasma enhanced chemical vapor deposition (PECVD) methods would theoretically largely avoid thermal excursion concerns when forming silicon oxide ion implant screen layers within microelectronic fabrications, silicon oxide ion implant screen layers formed employing plasma enhanced chemical vapor deposition (PECVD) methods nonetheless typically provide silicon oxide ion implant screen layers with compromised film thickness uniformity in comparison with silicon oxide ion implant screen layers formed employing thermal oxidation methods.
Thus, it is towards the goal of forming within a microelectronic fabrication a silicon containing dielectric layer, such as but not limited to a silicon oxide dielectric layer, which may be employed as an ion implant screen layer, where the silicon containing dielectric layer is formed with enhanced film thickness uniformity and with minimal temperature excursion, that the present invention is more specifically directed. In a more general sense, the present invention is also directed towards the goal of forming within microelectronic fabrications other microelectronic layers, such as but not limited to microelectronic conductor layers, microelectronic semiconductor layers and microelectronic dielectric layers with enhanced film thickness uniformity and minimal temperature excursion.
Various methods have been disclosed in the art of microelectronic fabrication for either: (1) forming silicon containing microelectronic layers with desirable properties within microelectronic fabrications; or (2) employing silicon containing microelectronic layers with desirable properties within microelectronic fabrications.
For example, Sze, in VLSI Technology, McGraw-Hill, N.Y. (1988), pp. 235-36, discloses various deposition methods and materials for forming silicon containing dielectric layers, as well as polysilicon layers, within microelectronic fabrications.
In addition, Cavanagh et al., in U.S. Pat. No. 4,567,645, discloses a method for forming with attenuated defect density a buried subcollector region for use within a semiconductor integrated circuit device formed within a semiconductor substrate. The method employs when forming the buried subcollector region while employing an ion implant method a silicon oxide ion implant screen layer which is partially stripped from a silicon semiconductor substrate within which is formed the buried subcollector region and then reoxidized to its original thickness after ion implanting the buried subcollector region within the silicon semiconductor substrate and prior to thermally annealing the silicon semiconductor substrate to repair damage within the silicon semiconductor substrate incurred incident to ion implanting the buried subcollector region within the silicon semiconductor substrate.
Further, Guldi, in U.S. Pat. No. 5,334,556, discloses a method for improving silicon oxide gate dielectric layer integrity within a silicon oxide gate dielectric layer formed within a field effect transistor (FET) employed within a semiconductor integrated circuit microelectronic fabrication. The method employs an oxidizing atmosphere, in part, when thermally annealing a pair of ion implanted source/drain regions within the field effect transistor (FET) within the semiconductor integrated circuit microelectronic fabrication.
Finally, Hsieh et al., in U.S. Pat. No. 5,482,876, discloses a method for forming within a semiconductor integrated circuit microelectronic fabrication while employing a (100) silicon semiconductor substrate a field effect transistor (FET) without spacer mask edge defects. The method employs when ion implanting a pair of source/drain regions within the (100) silicon semiconductor substrate within the field effect transistor (FET) within the semiconductor integrated circuit microelectronic fabrication while employing a gate electrode, a gate dielectric layer and a pair of dielectric spacer layers as a mask a ion implant screen layer formed thereupon, where an upper surface of the ion implant screen layer has an angle of elevation not exceeding 54.44 degrees with respect to the (100) silicon semiconductor substrate.
Desirable in the art of microelectronic fabrication are additional methods and materials for forming within microelectronic fabrications dielectric layers which may be employed as ion implant screen layers, where the dielectric layers are formed with enhanced film thickness uniformity and with minimal temperature excursion. More generally desirable in the art of microelectronic fabrication are additional methods and materials through which there may be formed within microelectronic fabrications microelectronic layers including but not limited to microelectronic conductor layers, microelectronic semiconductor layers and microelectronic dielectric layers, with enhanced film thickness uniformity and minimal temperature excursion.
It is towards the foregoing objects that the present invention is both specifically and more generally directed.